A Skein-512 Hardware Implementation
نویسندگان
چکیده
This paper describes our Skein-512 hardware implementation. Skein is a semi-finalist in the NIST hash competition to create SHA-3, with Skein-512 being the primary submission. We compare our implementation of Skein-512 with other published hardware implementations of Skein, and with similar implementations for SHA-1 and SHA-2. We discuss four variations of our critical path to explore the throughput/latency tradeoffs afforded by the Skein algorithm, with the best tradeoff offering throughput of 58Gbps at a latency of 20 clock cycles.
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